VHDL Macro: PS2

From JavierValcarce.Eu

You are at: Home > Hardware > VHDL Macro: PS2

Summary
This VHDL macro is a PS2 controller to connect a PS2 keyboard, mouse, etc. It is only a receiver, i.e., transmits data only in one direction (host $\leftarrow$ device)

VHDL Macro

xc3s400-4ft256 utilization
Element	Used
Slices	28
Flip-Flops	44
LUTs	31
Bonded IOBs	13
Global CLKs	1
Max Freq.	178.859MHz

component interface_ps2 
  port (
    reset   : in  std_logic;
    clk     : in  std_logic;
    kbdata  : in  std_logic;
    kbclk   : in  std_logic;
    newdata : out std_logic;
    do      : out std_logic_vector(7 downto 0)
    );
end component;

Ports and Usage

Port	DIR	Type	Description
reset	Input	signal	Asynchronous reset
clk	Input	signal	Clock signal, must be x4 faster at least than kbclk
kbdata	Output	signal	Serial PS2 data
kbclk	Output	signal	PS2 clock (~15kHz)
newdata	Output	signal	One clk cycle pulse, to raise an interrupt in PicoBlaze
do	Output	8-bit bus	Byte read from PS2 device

When a new data is available in do, a pulse (one clock cycle pulse) is present at newdata signal notifying the host circuit to transfer the octet to a FIFO buffer or something else. System clock clk must be faster (x4 or more) than kbclk (kbclk is about 15kHz).

Simulation

Cronogram in ModelSim for transmision of character 0x0F from keyboard to host

Download

Files:

interface_ps2.vhd
utils.vhd
interface_ps2_test.vhd Test Bench. Simulate it for 200 ns at least.

References

The PS/2 Mouse/Keyboard Protocol
"Diseño digital con lógica programable", 1º edición, Luis Jacobo Álvarez Ruiz de Ojeda, Tórculo Edicions, ISBN 84-8408-301-2