VHDL Macro: Epp2Fifo
From JavierValcarce.Eu
Summary
This VHDL macro is interface between Parallel Port (EPP mode) and a pair of fifos (TX/RX). When the host writes data ,no matter in what register, it is written in the RX fifo, when the host reads data, no matter in what register, it is read from TX fifo.
This VHDL macro is interface between Parallel Port (EPP mode) and a pair of fifos (TX/RX). When the host writes data ,no matter in what register, it is written in the RX fifo, when the host reads data, no matter in what register, it is read from TX fifo.
Table of Contents |
VHDL Macro
| Element | Used |
|---|---|
| Slices | 9 |
| Flip-Flops | 11 |
| LUTs | 19 |
| Bonded IOBs | 34 |
| Global CLKs | 1 |
| Max Freq. | 183.407MHz |
component epp2fifo port ( n_reset : in std_logic; clk : in std_logic; -- EPP interface epp_data : inout std_logic_vector(7 downto 0); epp_astb : in std_logic; epp_dstb : in std_logic; epp_write : in std_logic; epp_wait : out std_logic; -- 2-fifo interface tx_rd : out std_logic; tx_empty : in std_logic; tx_data : in std_logic_vector(7 downto 0); -- rx_wr : out std_logic; rx_full : in std_logic; rx_data : out std_logic_vector(7 downto 0)); end component;
Ports And Usage
The macro has the following ports:
| Port | Dir | Type | Description |
|---|---|---|---|
| n_reset | Input | signal | Asynchronous reset, active-low |
| clk | Input | signal | System clock |
| epp_data | IO | 08-bit bus | Bidirectional data bus |
| epp_astb | Input | signal | Address strobe |
| epp_dstb | Input | signal | Data strobe |
| epp_write | Input | signal | Write signal |
| epp_wait | Output | signal | Handshake and control-flow signal |
| tx_rd | Output | signal | TX fifo's rd signal |
| tx_empty | Input | signal | TX fifo's empty signal |
| tx_data | Output | 08-bit bus | TX fifo's data bus |
| rx_wr | Output | signal | RX fifo's wr signal |
| rx_full | Input | signal | RX fifo's full signal |
| rx_data | Output | 08-bit bus | RX fifo's data bus |
This block is a Parallel Port (EPP mode) to FIFO interface circuit. Its task is simple:
- all data sent by host (PC) is stored in the RX fifo (8-bit width data bus)
- all data read by host (PC) is obtained from the TX fifo (8-bit width data bus)
It is supposed that the fifos are standard (not First Word Fall Thought). The FSM blocks WAIT signal in case the RX fifo is full or TX fifo is empty, therefore, maintains the necessary control data flow, see parallel port spec. The epp_wait signal serves to control flow:
- If the operation initiated by host is read and there is no data available on TX fifo, the wait signal remains de-asserted until new data is available.
- If the operation initiated by host is write and there is no free space on RX fifo, the wait signal remains de-asserted until new data free space is available.